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this is information on a product in full production. october 2014 docid023214 rev 6 1/40 m95m01-a125 m95m01-a145 automotive 1 mbit serial spi bus eeproms with high-speed clock datasheet - production data features ? compatible with the serial peripheral interface (spi) bus ? memory array ? 1 mbit (128 kbytes) of eeprom ? page size: 256 bytes ? write protection by bl ock: 1/4, 1/2 or whole memory ? additional write lockable page (identification page) ? extended temperature and voltage ranges ? up to 125 c (v cc from 2.5 v to 5.5 v) ? up to 145 c (v cc from 2.5 v to 5.5 v) ? high speed clock frequency ? 16 mhz for v cc 4.5 v ? 10 mhz for v cc 2.5 v ? schmitt trigger inputs for noise filtering ? short write cycle time ? byte write within 4 ms ? page write within 4 ms ? write cycle endurance ? 4 million write cycles at 25 c ? 1.2 million write cycles at 85 c ? 600 k write cycles at 125 c ? 400 k write cycles at 145 c ? data retention ? 50 years at 125 c ? 100 years at 25 c ? esd protection (human body model) ? 4000 v ? packages ? rohs-compliant and halogen-free (ecopack2 ? ) so8 (mn) 150 mil width tssop8 (dw) 169 mil width www.st.com
contents m95m01-a125 m95m01-a145 2/40 docid023214 rev 6 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.8 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 hold mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 protocol control and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4.1 protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.2 status register and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 read identification page (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 write identification page (wrid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.9 read lock status (rdls) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.10 lock identification page (lid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
docid023214 rev 6 3/40 m95m01-a125 m95m01-a145 contents 3 5 application design recommendati ons . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.3 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 implementing devices on spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 cycling with error correction code (ecc) . . . . . . . . . . . . . . . . . . . . . . . . 28 6 delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of tables m95m01-a125 m95m01-a145 4/40 docid023214 rev 6 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. device identification bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. significant bits within the address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. cycling performance by groups of 4 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. operating conditions (voltage range w, temperatur e range 4). . . . . . . . . . . . . . . . . . . . . . 30 table 11. operating conditions (voltage range w, temperature range 3). . . . . . . . . . . . . . . . . . . . . . 30 table 12. operating conditions (volt age range w, temperature range 3) for high-speed communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. dc characteristics (voltage range w, temperature range 4). . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. dc characteristics (voltage range w, temperature range 3). . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. so8n ? 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 36 table 17. tssop8 ? 8-lead thin shrink small outline, pa ckage mechanical data. . . . . . . . . . . . . . . . 37 table 18. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
docid023214 rev 6 5/40 m95m01-a125 m95m01-a145 list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. hold mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. write enable (wren) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 6. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. read status register (rdsr) se quence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. read identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14. read lock status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. lock id sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 16. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. ac measurement i/o wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 20. serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 21. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 36 figure 22. tssop8 ? 8-lead thin shrink small outline, pa ckage outline . . . . . . . . . . . . . . . . . . . . . . . 37
description m95m01-a125 m95m01-a145 6/40 docid023214 rev 6 1 description the m95m01-a125 and m95m01-a145 are 1 -mbit serial eeprom automotive grade devices operating up to 145c. they are comp liant with the very high level of reliability defined by the automotive standard aec-q100 grade 0. the devices are accessed by a simple seri al spi compatible interface running up to 16 mhz. the memory array is based on advanced true eeprom technology (elect rically erasable programmable memory). the m95m01-a125 and m95m01-a145 are byte-alterable memories (131072 8 bits) organized as 512 page s of 256 bytes in which the data integrity is significantly improv ed with an embedded error correction code logic. the m95m01-a125 and m95m01-a145 offer an additional identification page (256 bytes) in which the st device identification can be re ad. this page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode. figure 1. logic diagram 069 ,k> ^ t }v??}oo}p] ,]pz}o?p pv??}? /lk?z](??p]??? ????p]??? v}v?? ? ?p]??? ?p y}? z}? y ^]}(?z z}vo? wzkd ? ^??? ?p]??? /v?](]?]}v?p le l?
docid023214 rev 6 7/40 m95m01-a125 m95m01-a145 description 39 figure 2. 8-pin package connections 1. see package mechanical data section for package dimensions and how to identify pin-1. table 1. signal names signal name description c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground $ 6 33 # (/,$ 1 36 ## 7 !)$ -xxx
signal description m95m01-a125 m95m01-a145 8/40 docid023214 rev 6 2 signal description all input signals must be held high or low (according to voltages of v ih or v il , as specified in table 13 and table 14 ). these signals are described below. 2.1 serial data output (q) this output signal is used to transfer data serially out of the device during a read operation. data is shifted out on the falling edge of serial clock (c), most significant bit (m sb) first. in all other cases, the serial data output is in high impedance. 2.2 serial data input (d) this input signal is used to transfer data serially into the device. d input receives instructions, addresses, and the data to be writ ten. values are latched on the rising edge of serial clock (c), most significant bit (msb) first. 2.3 serial clock (c) this input signal allows to sy nchronize the timing of the se rial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). 2.4 chip select (s ) driving chip select ( s ) low selects the device in order to start communication. driving chip select ( s ) high deselects the device and serial da ta output (q) enters the high impedance state. 2.5 hold (hold ) the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. 2.6 write protect (w ) this pin is used to write-protect the status register. 2.7 v ss ground v ss is the reference for all signals, including the v cc supply voltage.
docid023214 rev 6 9/40 m95m01-a125 m95m01-a145 signal description 39 2.8 v cc supply voltage v cc is the supply voltage pin. refer to section 3.1: active power and standby power modes and to section 5.1: supply voltage (vcc) .
operating features m95m01-a125 m95m01-a145 10/40 docid023214 rev 6 3 operating features 3.1 active power and standby power modes when chip select ( s ) is low, the device is selected and in the active power mode. when chip select ( s ) is high, the device is deselected. if a write cycle is not currently in progress, the device then goes in to the stan dby power mode, and the device consumption drops to i cc1 , as specified in table 13 and table 14 . 3.2 spi modes the device can be driven by a microcontroller wit h its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from t he falling edge of serial clock (c). the difference between the two modes, as shown in figure 3 , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 3. spi modes supported !)" # -3" #0(! $ #0/, 1 # -3"
docid023214 rev 6 11/40 m95m01-a125 m95m01-a145 operating features 39 3.3 hold mode the hold ( hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. the hold mode starts when the hold ( hold ) signal is driven low and the serial clock (c) is low (as shown in figure 4 ). during the hold mode, the se rial data output (q) is high impedance, and the signals present on serial data input (d) and serial clock (c) are not decoded. the hold mode ends when the hold ( hold ) signal is driven high and the serial clock (c) is or becomes low. figure 4. hold mode activation deselecting the device while it is in hold mode resets the paused communication. 3.4 protocol control and data protection 3.4.1 protocol control the chip select ( s ) input offers a built-in safety feature, as the s input is edge-sensitive as well as level-sensitive: after po wer-up, the device is not select ed until a falling edge has first been detected on chip select ( s ). this ensures that chip select ( s ) must have been high prior to going low, in order to start the first operation. for write commands (write, wrsr, wrid, lid) to be accepted and executed: ? the write enable latch (wel) bit must be se t by a write enable (wren) instruction ? a falling edge and a low st ate on chip select (s ) during the whole command must be decoded ? instruction, address and input data must be sent as multiple of eight bits ? the command must include at least one data byte ? chip select (s ) must be driven high exactly after a data byte boundary write command can be discarded at any time by a rising edge on chip select ( s ) outside of a byte boundary. to execute read commands (read, rdsr, rdid, rdls), the device must decode: ? a falling edge and a low level on chip select (s ) during the whole command ? instruction and address as multiples of eight bits (bytes) from this step, data bits are shifted out until the rising edge on chip select ( s ). (/,$ # (old condition # onditio n (old condition -36
operating features m95m01-a125 m95m01-a145 12/40 docid023214 rev 6 3.4.2 status register and data protection the status register format is shown in table 2 and the status and control bits of the status register are as follows: note: bits b6, b5, b4 are always read as 0. wip bit the wip bit (write in progress) is a read-only flag that indicates the ready/busy state of the device. when a write command (write, wrsr, wrid, lid) has been decoded and a write cycle (t w ) is in progress, the device is busy and the wip bit is set to 1. when wip=0, the device is ready to decode a new command. during a write cycle, reading continuously th e wip bit allows to detect when the device becomes ready (wip=0) to decode a new command. wel bit the wel bit (write enable latch) bit is a flag that indicates the status of the internal write enable latch. when wel is set to 1, the writ e instructions (write, wrsr, wrid, lid) are executed; when wel is set to 0, any decoded write instruction is not executed. the wel bit is set to 1 with the wren instru ction. the wel bit is reset to 0 after the following events: ? write disable (wrdi) instruction completion ? write instructions (write, wrsr, wrid, li d) completion including the write cycle time t w ? power-up bp1, bp0 bits the block protect bits (bp1, bp0) are non-vol atile. bp1,bp0 bits define the size of the memory block to be protected against write instructions, as defined in table 2 . these bits are written with the write status register (wrsr) instruction, provided that the status register is not protected (refer to ? srwd bit and w input signal ?, on page 13 ). table 2. status register format b7 b6 b5 b4 b3 b2 b1 b0 srwd 0 0 0 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
docid023214 rev 6 13/40 m95m01-a125 m95m01-a145 operating features 39 srwd bit and w input signal the status register write disable (srwd) bi t is operated in conjunction with the write protect pin ( w ) signal. when the srwd bit is written to 0, it is possible to write the status register, regardless of whether the pin write protect ( w ) is driven high or low. when the srwd bit is written to 1, two ca ses have to be considered, depending on the state of the w input pin: ? case 1: if pin w is driven high, it is possibl e to write the status register. ? case 2: if pin w is driven low, it is not possible to write the status register (wrsr is discarded) and therefore srwd,bp1,bp0 bits cannot be changed (the size of the protected memory block defined by bp1,bp0 bits is frozen). case 2 can be entered in either sequence: ? writing srwd bit to 1 after driving pin w low, or ? driving pin w low after writing srwd bit to 1. the only way to exit case 2 is to pull pin w high. note: if pin w is permanently tied high, the status register cannot be write-protected. the protection features of the device are summarized in table 4 . 3.5 identification page the m95m01-a125 and m95m01-a145 offer an ident ification page (256 bytes) in addition to the 1 mbit memory. the identification page contains two fields: ? device identification: the three first byte s are programmed by stmicroelectronics with the device identification code, as shown in table 5 . ? application parameters: the bytes after the de vice identification code are available for application specific data. table 3. write-protected block size status register bits protected block protected array addresses bp1 bp0 0 0 none none 0 1 upper quarter 1.80.00h - 1.ff.ffh 1 0 upper half 1.00.00h - 1.ff.ffh 1 1 whole memory 0.00.00h - 1ff.ffh plus identification page table 4. protection modes srwd bit w signal status 0x status register is writable. 11 1 0 status register is write-protected.
operating features m95m01-a125 m95m01-a145 14/40 docid023214 rev 6 note: if the end application does not need to read the device identification code, this field can be overwritten and used to store application-spec ific data. once the app lication-specific data are written in the identification page, the whol e identification page should be permanently locked in read-only mode. the read, write, lock identificati on page instructions are detailed in section 4: instructions . table 5. device id entification bytes address in identification page content value 00h st manufacturer code 20h 01h spi family code 00h 02h memory density code 11h (1 mbit)
docid023214 rev 6 15/40 m95m01-a125 m95m01-a145 instructions 39 4 instructions each command is composed of bytes (msbit tran smitted first), initiate d with the instruction byte, as summarized in table 6 . if an invalid instruction is sent (one not contained in table 6 ), the device automatically enters a wait state until deselected. for read and write commands to memory array and identification page, the address is defined by three bytes as explained in table 7 . table 6. instruction set instruction description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 rdid read identification page 1000 0011 wrid write identification page 1000 0010 rdls reads the identification page lock status. 1000 0011 lid locks the identific ation page in read- only mode. 1000 0010 table 7. significant bits within the address bytes (1) (2) instruction upper address byte b23 b22 ... b17 b16 middle address byte b15 b14 ... b10 b9 b8 lower address byte b7 b6 ... b2 b1 b0 read or write x x ... x a16 a15 a1 4 ... a10 a9 a8 a7 a6 ... a1 a0 rdid or wrid 0 0 ... 0 0 0 0 ... 0 0 0 a7 a6 ... a1 a0 rdls or lid 0 0 ... 0 0 0 0 0 0 . 0 1 0 0 0 0 ... 0 0 1. a: significant address bit. 2. x: bit is don?t care.
instructions m95m01-a125 m95m01-a145 16/40 docid023214 rev 6 4.1 write enable (wren) the wren instruction must be decoded by t he device before a write instruction (write, wrsr, wrid or lid). as shown in figure 5 , to send this instruction to the device, chip select ( s ) is driven low, the bits of the instruction byte are shifted in (msb first) on serial data input (d) after what the chip select ( s ) input is driven high and the wel bit is set (status register bit). figure 5. write enable (wren) sequence 4.2 write disable (wrdi) one way of resetting the wel bit (in the st atus register) is to send a write disable instruction to the device. as shown in figure 6 , to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in (msb first), on serial data input (d), after what the chip select ( s ) input is driven high and the wel bit is reset (status register bit). if a write cycle is currently in progress, the w rdi instruction is dec oded and executed and the wel bit is reset to 0 with no effect on the ongoing write cycle. figure 6. write disable (wrdi) sequence dlyj ^ y ? ?e? ,]pz/u?v /v????]}v # $ !)d 3 1 (igh)mpedance )nstruction
docid023214 rev 6 17/40 m95m01-a125 m95m01-a145 instructions 39 4.3 read status register (rdsr) the read status register (rdsr) instruction is used to read the content of the status register. as shown in figure 7 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte are shift ed in (msb first) on serial data input (d), the status register content is then shifted ou t (msb first) on serial data output (q). if chip select ( s ) continues to be driven low, the stat us register content is continuously shifted out. the status register can always be read, even if a write cycle (t w ) is in progress. the status register functionality is detailed in section 3.4.2: status register and data protection . figure 7. read status register (rdsr) sequence # $ 3 )nstruction !)% 1 3tatus2egister/ut (igh)mpedance -3" 3tatus2egister/ut -3"
instructions m95m01-a125 m95m01-a145 18/40 docid023214 rev 6 4.4 write status register (wrsr) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruct ion must previously have been executed. the write status register (wrsr) instruction is entered (msb fi rst) by driving chip select ( s ) low, sending the instruction code followed by the data byte on serial data input (d), and driving the chip select ( s ) signal high. the contents of the srwd and bp1, bp0 bits are updated after the completion of the wrsr instruction, incl uding the write cycle (t w ). the write status register (wrsr) instruction has no effect on the b6, b5, b4, b1 and b0 bits in the status register (see table 2: status register format ). the status register functionality is detailed in section 3.4.2: status register and data protection . the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. figure 8. write status register (wrsr) sequence # $ !)d 3 1 (igh)mpedance )nstruction 3tatus 2egister)n -3"
docid023214 rev 6 19/40 m95m01-a125 m95m01-a145 instructions 39 4.5 read from memory array (read) the read instruction is used to read the content of the memory. as shown in figure 9 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte and address byte s are shifted in (msb first) on serial data input (d) and the addressed data byte is then sh ifted out (msb first) on serial data output (q). the first addressed byte can be any byte within any page. if chip select ( s ) continues to be driven low, the internal address register is automatically incremented, and the next byte of data is shifted out. the whole memory can therefore be read with a single read instruction. when the highest address is reached, the addr ess counter rolls over to zero, a llowing the read cycle to be continued indefinitely. the read cycle is terminated by driving chip select ( s ) high at any time when the data bits are shifted out on serial data output (q). the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. figure 9. read from memory array (read) sequence 1. depending on the memory size, as shown in table 7 , the most significant address bits are don?t care. c d ai13878 s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
instructions m95m01-a125 m95m01-a145 20/40 docid023214 rev 6 4.6 write to memo ry array (write) the write instruction is used to write new data in the memory. as shown in figure 10 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte, address bytes, and at least one data byte are then shifted in (msb first), on serial data input (d). the instruction is term inated by driving chip select ( s ) high at a data byte boundary. figure 10 shows a single byte write. figure 10. byte write (write) sequence 1. depending on the memory size, as shown in table 7 , the most significant addr ess bits are don?t care. a page write is used to write several bytes insi de a page, with a single internal write cycle. for a page write, chip select ( s ) has to remain low, as shown in figure 11 , so that the next data bytes are shifted in. each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. if the address counter exceeds the page boundary (the page size is 256 bytes), the internal address pointer rolls over to the beginning of the same page where next data byte s will be written. if more than 256 bytes are received, only the last 256 bytes are written. for both byte write and page write, the self-timed write cycle starts from the rising edge of chip select ( s ), and continues for a period t w (as specified in table 15 ). the instruction is discarded, and is no t executed, under the following conditions: ? if a write cycle is already in progress ? if the addressed page is in the region protected by the block protect (bp1 and bp0) bits ? if one of the conditions defined in section 3.4.1 is not satisfied note: the self-timed write cycle t w is internally executed as a sequence of two consecutive events: [erase addressed byte(s)], followed by [program addressed byte(s)]. an erased bit is read as ?0? and a programmed bit is read as ?1?. -36 # $ 3 1 (ighimpedance )nstruction bitaddress $atabyte
docid023214 rev 6 21/40 m95m01-a125 m95m01-a145 instructions 39 figure 11. page write (write) sequence 1. depending on the memory size, as shown in table 7 , the most significant address bits are don?t care. -36 & ' 6 & ' 6 ,qvwuxfwlrq elwdgguhvv 'dwde\wh 'dwde\wh 'dwde\wh 'dwde\wh1
instructions m95m01-a125 m95m01-a145 22/40 docid023214 rev 6 4.7 read identification page (rdid) the read identification page instruction is used to read the identification page (additional page of 256 bytes which can be written and later permanently locked in read-only mode). the chip select ( s ) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in (msb fi rst) on serial data input (d). address bit a10 must be 0 and the other upper address bits are don't care (it might be easier to define these bits as 0, as shown in table 7 ). the data byte pointed to by the lower address bits [a7:a0] is shifted out (msb first) on serial data output (q). the first byte addressed can be any byte within the identification page. if chip select ( s ) continues to be driven low, the internal address register is automatically incremented and the byte of data at the new address is shifted out. note that there is no roll over feature in the identification page. the address of bytes to read must not exceed the page boundary. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time when the data bits are shifted out. the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. figure 12. read identification page sequence the first three bytes of the identification pa ge offer information about the device itself. please refer to section 3.5: identification page for more information. -36 # $ 3 1 (ighimpedance $ata/ut )nstruction bitaddress -3" -3" $ata/ut
docid023214 rev 6 23/40 m95m01-a125 m95m01-a145 instructions 39 4.8 write identification page (wrid) the write identification page instruction is used to write the identification page (additional page of 256 bytes which can also be permanently locked in read-only mode). the chip select signal ( s ) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (msb first) on serial data input (d). address bit a10 must be 0 and the other upper address bits are don't care (it might be easier to define these bits as 0, as shown in table 7 ). the lower address bits [a7:a0] define the byte address inside the identification page. the self-timed write cycle starts from the rising edge of chip select ( s ), and continues for a period t w (as specified in table 15 ). figure 13. write identification page sequence note: the first three bytes of the identification page offer the devi ce identification code (please refer to section 3.5: identification page for more information). us ing the wrid command on these first three bytes overwrites the device identification code. the instruction is discarded, and is no t executed, under the following conditions: ? if a write cycle is already in progress ? if the block protect bits (bp1,bp0) = (1,1) ? if one of the conditions defined in section 3.4.1: protocol control is not satisfied. 4.9 read lock status (rdls) the read lock status instruction is used to read the lock status. to send this instruction to the device, chip select ( s ) first has to be driven low. the bits of the instruction byte and address bytes are then shifted in (msb first) on serial data input (d). address bit a10 must be 1; all other addres s bits are don't care (it might be easier to define these bits as 0, as shown in table 7 ). the lock bit is the lsb (least significant bit) of the byte read on serial data output (q). it is at ?1? when the lock is active and at ?0? when the lock is not active. if chip select ( s ) continues to be driven low, the same data byte is shifted out. the read cycle is terminated by driving chip select ( s ) high. the instruction sequence is shown in figure 14 . -36 # $ 3 1 (ighimpedance )nstruction bitaddress $atabyte
instructions m95m01-a125 m95m01-a145 24/40 docid023214 rev 6 the read lock status instruction is not accepted and not executed if a write cycle is currently in progress. figure 14. read lock status sequence 4.10 lock identifi cation page (lid) the lock identification page (lid) command is used to permanently lock the identification page in read-only mode. the lid instruction is issued by driving ch ip select (s) low, sending (msb first) the instruction code, the address and a data byte on serial data input (d), and driving chip select (s) high. in the address sent, a10 must be equal to 1. all other address bits are don't care (it might be easier to define these bits as 0, as shown in table 7 ). the data byte sent must be equal to the binary value xxxx xx1x, where x = don't care. the lid instruction is terminated by driving chip select (s) high at a data byte boundary, otherwise, the instruction is not executed. figure 15. lock id sequence -36 # $ 3 1 (ighimpedance $ata/ut )nstruction bitaddress -3" -3" $ata/ut -36 # $ 3 1 (ighimpedance )nstruction bitaddress $atabyte
docid023214 rev 6 25/40 m95m01-a125 m95m01-a145 instructions 39 driving chip select ( s ) high at a byte boundary of the input data triggers the self-timed write cycle which duration is t w (specified in table 15 ). the instruction sequence is shown in figure 15 . the instruction is discarded, and is no t executed, under the following conditions: ? if a write cycle is already in progress ? if the block protect bits (bp1,bp0) = (1,1) ? if one of the conditions defined in section 3.4.1: protocol control is not satisfied.
application design recommendations m95m01-a125 m95m01-a145 26/40 docid023214 rev 6 5 application design recommendations 5.1 supply voltage (v cc ) 5.1.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc(min) , v cc(max) ] range must be applied (see table 10 and table 11 ). this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. 5.1.2 power-up conditions when the power supply is turned on, v cc continuously rises from v ss to v cc . during this time, the chip select ( s ) line is not allowed to float but should follow the v cc voltage. it is therefore recommended to connect the s line to v cc via a suitable pull-up resistor (see figure 16 ). the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined in table 13 and table 14 . in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not re spond to any instruction until v cc reaches the internal threshold voltage (this threshold is defined in the dc characteristics tables 13 and 14 as vres). when v cc passes over the por threshold, the device is reset and in the following state: ? in the standby power mode ? deselected ? status register values: ? write enable latch (w el) bit is reset to 0. ? write in progress (wip) bit is reset to 0. ? srwd, bp1 and bp0 bits remain unchanged (non-volatile bits). ? not in the hold condition as soon as the v cc voltage has reached a stable value within [v cc (min), v cc (max)] range, the device is ready for operation.
docid023214 rev 6 27/40 m95m01-a125 m95m01-a145 application design recommendations 39 5.1.3 power-down during power-down (continuous decrease in the v cc supply voltage below the minimum v cc operating voltage defined in table 13 and table 14 ), the device must be: ? deselected (chip select (s ) should be allowed to follo w the voltage applied on v cc ), ? in standby power mode (there should not be any internal write cycle in progress). 5.2 implementing d evices on spi bus figure 16 shows an example of three devices, connected to the spi bus master. only one device is selected at a time, so that only th e selected device drives the serial data output (q) line. all the other devices outputs are then in high impedance. figure 16. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals must be driven high or low as appropriate. a pull-up resistor connected on each / s input (represented in figure 16 ) ensures that each device is not selected if the bus master leaves the / s line in the high impedance state. 30)busmaster 3$/ 3$) 3#+ #1$ #1$ #1$ #3 #3 #3 30)interfacewith #0/,#0(! or 30)memory device 3 7 (/,$ 222 6 ## 6 ## 6 ## 6 ## -36 6 33 30)memory device 3 7 (/,$ 30)memory device 3 7 (/,$
application design recommendations m95m01-a125 m95m01-a145 28/40 docid023214 rev 6 5.3 cycling with error correction code (ecc) the error correction code (ecc) is an internal logic function which is transparent for the spi communication protocol. the ecc logic is implemented on each group of four eeprom bytes (a) . inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ecc detects this bit and replaces it with the correct value. the read reliability is therefore much improved. even if the ecc function is performed on group s of four bytes, a single byte can be written/cycled independently. in this case, th e ecc function also writes/cycles the three other bytes located in the same group (a) . as a consequence, the maximum cycling budget is defined at group level and the cycling can be di stributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in table 9: cycling performance by groups of 4 bytes . example1: maximum cycling limit reached with 1 million cycles per byte each byte of a group can be e qually cycled 1 million times (at 25 c) so that the group cycling budget is 4 million cycles. example2: maximum cycling limit reached with unequal byte cycling inside a group, byte0 can be cycled 2 million times, by te1 can be cycled 1 million times, byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million cycles. a. a group of four bytes is located at addresses [4 *n, 4*n+1, 4*n+2, 4*n+3], where n is an integer.
docid023214 rev 6 29/40 m95m01-a125 m95m01-a145 delivery state 39 6 delivery state the device is delivered with: ? the memory array set to all 1s (each byte = ffh), ? status register: bit srwd =0, bp1 =0 and bp0 =0, ? identification page: the first three bytes def ine the device identification code (value defined in table 5 ). the content of the following bytes is don?t care. 7 absolute maximum ratings stressing the device outside the ratings listed in table 8 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 8. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c t amr ambient operating temperature ?40 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020d (for small b ody, sn-pb or pb-free assembly), the st ecopack ? 7191395 specification, and the european directive on re strictions of hazardous substances (rohs directive 2011/65/eu of july 2011). c v o voltage on q pin ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v i ol dc output current (q = 0) - 5 ma i oh dc output current (q = 1) - 5 ma v cc supply voltage ?0.50 6.5 v v esd electrostatic pulse (human body model) (2) 2. positive and negative pulses applied on pin pairs, in accordance with aec -q100-002 (compliant with ansi/esda/jedec js-001-2012, c1=100 pf, r1=1500 , r2=500 ) -4000v
dc and ac parameters m95m01-a125 m95m01-a145 30/40 docid023214 rev 6 8 dc and ac parameters this section summarizes the operating condi tions and the dc/ac characteristics of the device. table 9. cycling performance by groups of 4 bytes symbol parameter test condition min. max. unit ncycle write cycle endurance (1) ta 25 c, 2.5 v < v cc < 5.5 v - 4,000,000 write cycle (2) ta = 85 c, 2.5 v < v cc < 5.5 v - 1,200,000 ta = 125 c, 2.5 v < v cc < 5.5 v - 600,000 ta = 145 c (3) , 2.5 v < v cc < 5.5 v - 400,000 1. the write cycle endurance is defined for groups of four data by tes located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3] where n is an integer, or for the status register byte (refer also to section 5.3: cycling with error correction code (ecc) ). the write cycle endurance is defined by characterization and qualification. 2. a write cycle is executed when either a page write, a by te write, a wrsr, a wrid or an lid instruction is decoded. when using the byte write, the page write or the wrid, refer also to section 5.3: cycling with error correction code (ecc) . 3. for temperature range 4 only. table 10. operating conditions (voltage range w, temperature range 4) symbol parameter conditions min. max. unit v cc supply voltage - 2.5 5.5 v t a ambient operating temperature - ?40 145 c f c operating clock frequency 5.5 v v cc 2.5 v, capacitive load on q pin 100pf -10mhz table 11. operating conditions (voltage range w, temperature range 3) symbol parameter conditions min. max. unit v cc supply voltage - 2.5 5.5 v t a ambient operating temperature - ?40 125 c f c operating clock frequency v cc 2.5 v, capacitive load on q pin 100pf - 10 mhz table 12. operating conditions (voltage range w, temperature range 3) for high-speed communications symbol parameter conditions min. max. unit v cc supply voltage - 4.5 5.5 v t a ambient operating temperature - ?40 85 c f c operating clock frequency v cc 4.5 v, capacitive load on q pin 60 pf - 16 mhz
docid023214 rev 6 31/40 m95m01-a125 m95m01-a145 dc and ac parameters 39 table 13. dc characteristics (voltage range w, temperature range 4) symbol parameter specific test conditions (in addition to conditions specified in table 10 ) min. max. unit c out (2) output capacitance (q) v out = 0 v - 8 pf c in (2) input capacitance v in = 0 v - 6 i li input leakage current v in = v ss or v cc -2 a i lo output leakage current s = v cc , v out = v ss or v cc -3 i cc supply current (read) v cc = 2.5 v, f c = 10 mhz, c = 0.1 v cc /0.9 v cc, q = open -2 ma v cc = 5.5 v, f c = 10 mhz, c = 0.1 v cc /0.9 v cc, q = open -4 i cc0 (1) supply current (write) 2.5 v < v cc < 5.5 v, during t w , s = v cc -2 (2) i cc1 supply current (standby power mode) t = 85 c, v cc = 2.5 v, s = v cc v in = v ss or v cc -2 a t = 85 c, v cc = 5.5 v, s = v cc v in = v ss or v cc -3 t = 125 c, v cc = 2.5 v, s = v cc v in = v ss or v cc -15 t = 125 c, v cc = 5.5 v, s = v cc v in = v ss or v cc -20 t = 145 c, v cc = 2.5 v, s = v cc v in = v ss or v cc -25 t = 145 c, v cc = 5.5 v, s = v cc v in = v ss or v cc -40 v il input low voltage - ?0.45 0.3 v cc v v ih input high voltage - 0.7 v cc v cc +1 v ol output low voltage i ol = 2 ma - 0.4 v oh output high voltage i oh = ?2 ma 0.8 v cc - v res (2) internal reset threshold voltage -0.51.5 1. average value during the write cycle (t w ) 2. characterized only, not 100% tested
dc and ac parameters m95m01-a125 m95m01-a145 32/40 docid023214 rev 6 table 14. dc characteristics (voltage range w, temperature range 3) symbol parameter test conditions (in addition to co nditions specified in table 11 ) min. max. unit c out (3) output capacitance (q) v out = 0 v - 8 pf c in (3) input capacitance v in = 0 v - 6 i li input leakage current v in = v ss or v cc -2 a i lo output leakage current s = v cc , v out = v ss or v cc -3 i cc supply current (read) v cc = 2.5 v, c = 0.1v cc /0.9 v cc , q = open f c = 10 mhz -2 ma v cc = 5.5 v, f c = 16 mhz (1) c = 0.1 v cc /0.9 v cc , q = open -5 i cc0 (2) supply current (write) 2.5 v v cc < 5.5 v during t w , s = v cc -2 (3) ma i cc1 supply current (standby mode) t = 85 c, v cc = 2.5 v, s = v cc, v in = v ss or v cc -2 a t = 85 c, v cc = 5.5 v, s = v cc, v in = v ss or v cc -3 t = 125 c, v cc = 2.5 v, s = v cc, v in = v ss or v cc -15 t = 125 c, vcc = 5.5 v, s = v cc , v in = v ss or v cc -20 v il input low voltage 2.5 v v cc < 5.5 v ?0.45 0.3 v cc v v ih input high voltage 2.5 v v cc < 5.5 v 0.7 v cc v cc + 1 v v ol output low voltage v cc 2.5 v, i ol = 2 ma - 0.4 v v oh output high voltage v cc 2.5 v, i oh = -2 ma 0.8 v cc -v v res (3) internal reset threshold voltage - 0.5 1.5 v 1. when ?40 c < t < 85 c. 2. average value during the write cycle (t w ) 3. characterized only, not 100% tested
docid023214 rev 6 33/40 m95m01-a125 m95m01-a145 dc and ac parameters 39 table 15. ac characteristics symbol alt. parameter min. max. min. max. unit test conditions specified in table 10 and table 11 test conditions specified in table 12 f c f sck clock frequency 10 16 mhz t slch t css1 s active setup time 30 20 ns t shch t css2 s not active setup time 30 20 t shsl t cs s deselect time 40 25 t chsh t csh s active hold time 30 20 t chsl s not active hold time 30 20 t ch (1) 1. t ch + t cl must never be lower than the shortest possible clock period, 1/f c (max). t clh clock high time 40 25 t cl (1) t cll clock low time 40 25 t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 2 2 s t chcl (2) t fc clock fall time 2 2 t dvch t dsu data in setup time 10 10 ns t chdx t dh data in hold time 10 10 t hhch clock low hold time after hold not active 30 25 t hlch clock low hold time after hold active 30 20 t clhl clock low set-up time before hold active 0 0 t clhh clock low set-up time before hold not active 00 t shqz (2) t dis output disable time 40 25 t clqv (3) 3. t clqv must be compatible with t cl (clock low time): if t su is the read setup time of the spi bus master, t cl must be equal to (or greater than) t clqv +t su . t v clock low to output valid 40 25 t clqx t ho output hold time 0 0 t qlqh (2) t ro output rise time 20 25 t qhql (2) t fo output fall time 20 25 t hhqv t lz hold high to output valid 40 25 t hlqz (2) t hz hold low to output high-z 40 25 t w t wc write time 4 4 ms
dc and ac parameters m95m01-a125 m95m01-a145 34/40 docid023214 rev 6 figure 17. ac measurement i/o waveform figure 18. serial input timing figure 19. hold timing !)# 6 ## 6 ## 6 ## 6 ## )nputandoutput timingreferencelevels )nputvoltagelevels # $ !)d 3 -3"). 1 t$6#( (ighimpedance ,3"). t3,#( t#($8 t#,#( t3(#( t3(3, t#(3( t#(3, t#( t#, t#(#, # 1 !)c 3 1 t#,(, t(,#( t((#( t#,(( t((16 t(,1:
docid023214 rev 6 35/40 m95m01-a125 m95m01-a145 dc and ac parameters 39 figure 20. serial output timing # 1 !)f 3 $ !$$2 ,3"). t3(1: t#( t#, t1,1( t1(1, t#(#, t#,18 t#,16 t3(3, t#,#(
package mechanical data m95m01-a125 m95m01-a145 36/40 docid023214 rev 6 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and prod uct status are available at: www.st.com. ecopack ? is an st trademark. figure 21. so8n ? 8-lead plas tic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 16. so8n ? 8-lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ. min. max. typ. min. max. a - - 1.75 - - 0.0689 a1 - 0.10 0.25 - 0.0039 0.0098 a2 - 1.25 - - 0.0492 - b - 0.28 0.48 - 0.011 0.0189 c - 0.17 0.23 - 0.0067 0.0091 ccc - - 0.10 - - 0.0039 d 4.90 4.80 5.00 0.1929 0.189 0.1969 e 6.00 5.80 6.20 0.2362 0.2283 0.2441 e1 3.90 3.80 4.00 0.1535 0.1496 0.1575 e 1.27 - - 0.05 - - h - 0.25 0.50 - 0.0098 0.0197 k-08-08 l - 0.40 1.27 - 0.0157 0.05 l1 1.04 - - 0.0409 - - 62$b9 ( fff e ' f ( k[? $ n pp / $ *$8*(3/$1( h $ /
docid023214 rev 6 37/40 m95m01-a125 m95m01-a145 package mechanical data 39 figure 22. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 17. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ. min. max. typ. min. max. a - - 1.200 - - 0.0472 a1 - 0.050 0.150 - 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b - 0.190 0.300 - 0.0075 0.0118 c - 0.090 0.200 - 0.0035 0.0079 cp - - 0.100 - - 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 - - 0.0394 - - -08-08 76623$0b9 w > r e > ? ??
part numbering m95m01-a125 m95m01-a145 38/40 docid023214 rev 6 10 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 18. ordering information scheme example: m95m01-d w dw 4 t p /k device type m95 = spi serial access eeprom device function m01-d = 1 mbit (128 kbytes ) plus identification page operating voltage w = v cc = 2.5 to 5.5 v package (1) 1. all packages are ecopack2 ? (rohs compliant and free of brominated, chlorinated and antimony-oxide flame retardants). mn = so8 (150 mils width) dw = tssop8 (169 mils width) device grade 3 = ?40 to 125 c. device tested with high reliability certified flow (2) 2. the high reliability cert ified flow (hrcf) is described in quality note qnee9801. please ask your nearest st sales office for a copy. 4 = ?40 to 145 c. device tested with high reliability certified flow (2) option blank = tube packing t = tape and reel packing plating technology p or g = ecopack2 ? process letter /k = manufacturing technology code
docid023214 rev 6 39/40 m95m01-a125 m95m01-a145 revision history 39 11 revision history table 19. document revision history date revision changes 06-jun-2012 1 initial release. 30-jul-2012 2 ?v cc range r3 replaced with range w3 ? max clock frequency defined as 16 mhz when v cc > 4.5 v inside the [-40 c / +85 c] temperature range 14-feb-2013 3 ? removed ufdfpn8 (mlp8) package. ? updated v res maximum value in table 13: dc characteristics (voltage range w, temperature range 4) and table 14: dc characteristics (voltage range w, temperature range 3) . ? rephrased introduction of section 3.5: identification page and information about identification page in section 6: delivery state . ? deleted note (1) under table 6: instruction set . 10-apr-2013 4 document reformatted. document status changed from ?p reliminary data? to ?production data?. updated note (1) under table 8: absolute maximum ratings . 04-feb-2014 5 changed data retention from ?40 years at 55 c? to ?50 years at 125 c? in features . removed bullets in section 4.2: write disable (wrdi) (refer to section : wel bit ). removed redundant sentence after table 5: device identification bytes . 31-oct-2014 6 updated note 2 below table 8: absolute maximum ratings updated table 14: dc characteristics (v oltage range w, temperature range 3) updated table 18: ordering information scheme
m95m01-a125 m95m01-a145 40/40 docid023214 rev 6 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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